The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) has traditionally been orders of magnitude faster in both latency and bandwidth than persistent storage (e.g., magnetic disk, Flash, etc.). However, volatile memory may come at a higher cost/bit and therefore a more limited capacity when compared with persistent storage. Given these limitations and strengths of volatile memory versus persistent storage, computing systems have traditionally organized them into a tiered architecture. In such an architecture, volatile memory may be directly coupled with a central processing unit (CPU) (e.g., via a memory bus) of a computing device and hence may be directly accessible by instructions of the CPU. Persistent storage, on the other hand, may be coupled with the CPU through an input/output (I/O) controller (e.g., small computer system interface (SCSI), serial advanced technology attachment (SATA), peripheral component interconnect (PCI)-Express, etc.). As a result, volatile memory may be in the CPU's address domain but persistent storage may be in the CPU's I/O controller's address domain. Such a configuration may require an operating system to manage the volatile memory and the persistent storage as distinct volatile and storage domains, respectively. This may lead to certain inefficiencies and additional processes, for example, when loading a data item from persistent storage to volatile memory for access by the CPU.